Abstract
Symbolic reachability analysis based on Binary Decision Diagrams (BDDs) is a technique that allows the implementation of efficient state space exploration algorithms. However, in practice it is well known that the BDD blowup problem limits the size of the systems that can be analyzed. Conversely, simulation is a low-cost state generation technique, although its effectiveness is limited due to its inherent sequentiality. We present a hybrid methodology that combines simulation and symbolic traversal in order to improve the state space exploration of large systems. The methodology concentrates on asynchronous concurrent systems, whose peculiarities are not fully exploited by other existing techniques for hybrid verification. Our approach exploits the information obtained from simulations to improve the knowledge of the state space, effectively guiding symbolic traversal. We demonstrate the applicability of this methodology in the verification of complex control-dominated asynchronous circuits.
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Funded by the Ministry of Science and Technology of Spain TIC 2001-2476-C03-02 and DURSI of Generalitat de Catalunya 2001SGR-00226.
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Pastor, E., Peña, M.A. (2003). Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems. In: Geist, D., Tronci, E. (eds) Correct Hardware Design and Verification Methods. CHARME 2003. Lecture Notes in Computer Science, vol 2860. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39724-3_33
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DOI: https://doi.org/10.1007/978-3-540-39724-3_33
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