Abstract
In this paper a Globally Asynchronous Locally Synchronous (GALS) implementation of a complex digital system is discussed. The deployed asynchronous wrappers are based on a novel request-driven technique with embedded time-out function. Each GALS block is fitted with a local clock generator for flushing the internal pipeline stages when there are no incoming requests. This request-driven technique is applied for the ‘GALSification’ of an IEEE 802.11a compliant baseband processor. Details of the GALS partitioning and some additionally developed blocks will be discussed. Furthermore, the design-flow, implementation results and power estimation numbers are reported.
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Krstić, M., Grass, E. (2004). GALSification of IEEE 802.11a Baseband Processor. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_28
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DOI: https://doi.org/10.1007/978-3-540-30205-6_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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