Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor

Abstract

The cache size tends to grow in the embedded processor as technology scales to smaller transistors and lower supply voltages. However, larger cache size demands more energy. Accordingly, the ratio of the cache energy consumption to the total processor energy is growing. Many cache energy schemes have been proposed for reducing the cache energy consumption. However, these previous schemes are concerned with one side for reducing the cache energy consumption, dynamic cache energy only, or static cache energy only. In this paper, we propose a hybrid scheme for reducing dynamic and static cache energy, simultaneously. For this hybrid scheme, we adopt two existing techniques to reduce static cache energy consumption, drowsy cache technique, and to reduce dynamic cache energy consumption, way–prediction technique. Additionally, we propose a early wakeup technique based on instruction PC to reduce penalty caused by applying these two schemes. We focus on level 1 data cache. Our experimental evaluation shows the total extra cycles due to using drowsy cache scheme can be reduced by 29.6%, on average, through our suggested early wakeup scheme and the ratio of drowsy cache lines is over 87%. The total dynamic energy of the processor can be reduced by 2.2% to 6.8%. Energy-delay about total dynamic processor energy is, on average, reduced by 3% versus a processor using base cache scheme, not using any schemes for energy reduction.

This work was supported by the Brain Korea 21 Project.