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Parallel Sparse Matrix Vector Multiplication on Intel MIC: Performance Analysis

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Smart Societies, Infrastructure, Technologies and Applications (SCITA 2017)

Abstract

Numerous important scientific and engineering applications rely on and are hindered by, the intensive computational and storage requirements of sparse matrix-vector multiplication (SpMV) operation. SpMV also forms an important part of many (stationary and non-stationary) iterative methods for solving linear equation systems. Its performance is affected by factors including the storage format used to store the sparse matrix, the specific computational algorithm and its implementation. While SpMV performance has been studied extensively on conventional CPU architectures, research on its performance on emerging architectures, such as Intel Many Integrated Core (MIC) Architecture, is still in its infancy. In this paper, we provide a performance analysis of the parallel implementation of SpMV on the first-generation of Intel Xeon Phi Coprocessor, Intel MIC, named Knights Corner (KNC). We use the offload programming model to offload the SpMV computations to MIC using OpenMP. We measure the performance in terms of the execution time, offloading time and memory usage. We achieve speedups of up to 11.63x on execution times and 3.62x on offloading times using up to 240 threads compared to the sequential implementation. The memory usage varies depending on the size of the sparse matrix and the number of non-zero elements in the matrix.

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Acknowledgments

The experiments reported in this paper were performed on the Aziz supercomputer at King AbdulAziz University, Jeddah, Saudi Arabia.

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Authors and Affiliations

  1. Computer Science Department, Faculty of Computing and Information Technology, King Abdulaziz University, Jeddah, 21589, Kingdom of Saudi Arabia

    Hana Alyahya & Iyad Katib

  2. High-Performance Computing Center, King Abdulaziz University, Jeddah, Kingdom of Saudi Arabia

    Rashid Mehmood

Authors
  1. Hana Alyahya
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  2. Rashid Mehmood
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  3. Iyad Katib
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Corresponding author

Correspondence to Hana Alyahya .

Editor information

Editors and Affiliations

  1. King Abdulaziz University, Jeddah, Saudi Arabia

    Rashid Mehmood

  2. Geographic Information Science and Technology, Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA

    Budhendra Bhaduri

  3. King Abdulaziz University, Jeddah, Saudi Arabia

    Iyad Katib

  4. European Alliance for Innovation, Bratislava, Slovakia

    Imrich Chlamtac

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© 2018 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Alyahya, H., Mehmood, R., Katib, I. (2018). Parallel Sparse Matrix Vector Multiplication on Intel MIC: Performance Analysis. In: Mehmood, R., Bhaduri, B., Katib, I., Chlamtac, I. (eds) Smart Societies, Infrastructure, Technologies and Applications. SCITA 2017. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 224. Springer, Cham. https://doi.org/10.1007/978-3-319-94180-6_29

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  • DOI: https://doi.org/10.1007/978-3-319-94180-6_29

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-94179-0

  • Online ISBN: 978-3-319-94180-6

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