Abstract
Intrusion detection systems (IDS) are commonly utilized to prevent cyber-attacks. With the wide proliferation of network connected devices, running IDS algorithms on all devices (including mobile devices) within a network can help bolster security. However, the cost of running IDS algorithms on all networked devices can be high in terms of power and physical resources (especially battery operated ones). Several recent studies have proposed mapping applications to neural network form and then running these on specialized neural network accelerators [1, 2] to reduce power consumption. Neural accelerators can result in power reduction from about 2 times to several thousand times compared to RISC processors [3]. Hence utilizing these neural network accelerators can enabling the deployment of IDS algorithms across all devices in a network.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
B. Belhadj, A. J. L. Zheng, R. Héliot, and O. Temam. “Continuous real-world inputs can open up alternative accelerator designs,” SIGARCH Comput. Archit. News 41, 3 (June 2013)
Steve Esser, Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Davis Barch, Arnon Amir, John Arthur, Andrew Cassidy, Myron Flickner, Paul Merolla, Shyamal Chandra, Nicola Basilico, Stefano Carpin, Tom Zimmerman, Frank Zee, Rodrigo Alvarez-Icaza, Jeffrey Kusnitz, Theodore Wong, William Risk, Emmett McQuinn, Tapan Nayak, Raghavendra Singh and Dharmendra Modha, “Cognitive Computing Systems: Algorithms and Applications for Networks of Neurosynaptic Cores,” International Joint Conference on Neural Networks, Dallas, Texas, 2013.
T. Taha, R. Hasan, C. Yakopcic and M. McLean, “Exploring the Design Space of Specialized Multicore Neural Processors,” International Joint Conference on Neural Networks (IJCNN), August 2013. Available at: http://homepages.udayton.edu/~ttaha1/papers/IJCNN13_cores.pdf
T. Bass, “Intrusion detection systems and multisensor data fusion,”Communications of the ACM 43, no. 4 (2000): 99-105.
E. Marcello, C. Mazzariello, F. Oliviero, S. P. Romano, and C. Sansone, “Evaluating Pattern Recognition Techniques in Intrusion Detection Systems,” In PRIS, pp. 144-153. 2005.
N. Jiang, and Li Yu, “Intrusion detection using pattern recognition methods,” In Optics East 2007, pp. 67730S-67730S. International Society for Optics and Photonics, 2007.
L. O. Chua, “Memristor-The Missing Circuit Element,” IEEE Transactions on Circuit Theory, vol.18, no.5, pp 507-519, 1971.
D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing Memristor found,” Nature, 453, pp 80-83, 2008.
R. S. Williams, “How We Found The Missing Memristor,” IEEE Spectrum, vol. 45, no. 12, pp. 28-35, 2008.
C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, “Generalized Memristive Device SPICE Model and its Application in Circuit Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23 (2013) pp. 1201-1214.
H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, “Neural Acceleration for General-Purpose Approximate Programs,” International Symposium on Microarchitecture (MICRO), 2012.
H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, “Towards Neural Acceleration for General-Purpose Approximate Computing,” Workshop on Energy Efficient Design (WEED), 2012.
P. Merolla, J. Arthur, F. Akopyan, N. Imam, R. Manohar, D. S. Modha, “A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm,” IEEE Custom Integrated Circuits Conference (CICC) pp.1-4, 19-21 Sept. 2011.
J. V. Arthur, P. A. Merolla, F. Akopyan, R. Alvarez, A. Cassidy, S. Chandra, S. K. Esser, N. Imam, W. Risk, D. B. D. Rubin, R. Manohar, D. S. Modha, “Building block of a programmable neuromorphic substrate: A digital neurosynaptic core,” International Joint Conference on Neural Networks (IJCNN), pp.1-8, June 2012.
N. Muralimanohar, R. Balasubramonian, and N. Jouppi, “Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0” In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 40), Washington, DC, USA, 3-14, 2007.
A. B. Kahng, B. Li, L. S. Peh, and K. Samadi, “ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration,” Design, Automation & Test in Europe Conference & Exhibition, pp.423-428, 20-24 April 2009.
W. Lu, K.-H. Kim, T. Chang, S. Gaba, “Two-terminal resistive switches (memristors) for memory and logic applications,” Asia and South Pacific Design Automation Conference, pp. 217-223, 2011.
C. Yakopcic and T. M. Taha, “Energy Efficient Perceptron Pattern Recognition Using Segmented Memristor Cross-bar Arrays,” IEEE International Joint Conference on Neural Networks (IJCNN), August 2013.
S. Shin, K. Kim, S.-M. Kang, “Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs,” Proceedings of the IEEE, 100(6), June 2012.
B. Han, and T. M. Taha, “Acceleration of spiking neural network based pattern recognition on NVIDIA graphics processors,” Journal of Applied Optics, 49(101), pp. 83-91, 2010.
J. M. Nageswaran, N. Dutt, J. L. Krichmar, A. Nicolau, and A.Veidenbaum, “Efficient simulation of large-scale spiking neural networks using CUDA graphics processors,” In Proceedings of the 2009 international joint conference on Neural Networks (IJCNN). IEEE Press, Piscataway, NJ, USA, 3201-3208, 2009.
T. Chen, Y. Chen, M. Duranton, Q. Guo, A. Hashmi, M. Lipasti, A. Nere, S. Qiu, M. Sebag, O. Temam, “BenchNN: On the Broad Potential Application Scope of Hardware Neural Network Accelerators,” IEEE International Symposium on Workload Characterization (IISWC), November 2012.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Taha, T.M., Hasan, R., Yakopcic, C., McLean, M.R. (2014). Low Power Neuromorphic Architectures to Enable Pervasive Deployment of Intrusion Detection Systems. In: Pino, R., Kott, A., Shevenell, M. (eds) Cybersecurity Systems for Human Cognition Augmentation. Advances in Information Security, vol 61. Springer, Cham. https://doi.org/10.1007/978-3-319-10374-7_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-10374-7_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-10373-0
Online ISBN: 978-3-319-10374-7
eBook Packages: Computer ScienceComputer Science (R0)