Abstract
While gate level simulation precision is still required for certain tasks, its high simulation detail is rarely required throughout the total simulated duration. To overcome the low simulation performance that comes along with gate level simulation, we present an adaptive simulation approach allowing to choose between register transfer and gate level abstractions online during simulation. This is achieved by adaptive SystemC models encapsulating an RTL model and a synthesized gate level counterpart. Adaptive models multiplex between fixed abstraction models and efficiently perform the necessary state transfer, which is enabled by giving adaptive models limited access to the simulation kernel. Adaptivity works with almost any given RTL model and is established in an automated, seamless way. Simulation performance is further increased by the fine-grained selection of simulation precision on a submodule basis. The benefits of having spatial and temporal freedom to choose the abstraction level online during simulation have been confirmed in our evaluations where speedups of up to 150 times have been achieved.
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Notes
- 1.
The value of 2 determines the number of multiplexer inputs.
- 2.
Like std_logic_vector, signed and unsigned types from package ieee.numeric_std are arrays of std_logic. However, they have added numerical interpretation. signed and unsigned types are not to be confused with scalar types integer, natural or positive types!
- 3.
77 % CPU time compared to 80 % gate level simulation time.
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Acknowledgments
This work has been supported by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG) under grant Ra 1889/4-1.
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Eggenberger, M., Radetzki, M. (2015). Fine-Grained Adaptive Simulation. In: Louërat, MM., Maehne, T. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 311. Springer, Cham. https://doi.org/10.1007/978-3-319-06317-1_12
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