Abstract
We present the design of a Clifford algebra co-processor and its implementation on a Field Programmable Gate Array (FPGA). To the best of our knowledge this is the first such design developed. The design is scalable in both the Clifford algebra dimension and the bit width of the numerical factors. Both aspects are only limited by the hardware resources. Furthermore, the signature of the underlying vector space can be changed without reconfiguring the FPGA. High calculation speeds are achieved through a pipeline architecture.
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Perwass, C., Gebken, C., Sommer, G. (2004). Implementation of a Clifford Algebra Co-Processor Design on a Field Programmable Gate Array. In: Abłamowicz, R. (eds) Clifford Algebras. Progress in Mathematical Physics, vol 34. Birkhäuser Boston. https://doi.org/10.1007/978-1-4612-2044-2_35
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DOI: https://doi.org/10.1007/978-1-4612-2044-2_35
Publisher Name: Birkhäuser Boston
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Online ISBN: 978-1-4612-2044-2
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