Abstract
One of the main disadvantages of their sub-threshold circuits is their extreme sensitivity to variations in power supply, temperature and processing. In this chapter, we present a sub-threshold design methodology that automatically self-adjusts for inter and intra-die process, supply voltage and temperature (PVT) variations. This adjustment is achieved by performing bulk voltage adjustments in a closed-loop fashion. The design methodology uses medium-sized Programmable Logic Arrays (PLAs) as the circuit implementation structure. Details about the structure and operation of the PLAs are presented in Sect. 10.3. The design has a global beat clock to which the delay of a spatially localized cluster of PLAs is “phase locked”. The synchronization is performed in a closed-loop fashion, using a phase detector and a charge pump that drives the bulk nodes of the PLAs in the cluster. The details of this scheme are presented in Sect. 10.4. The experimental results presented in Sect. 10.5 demonstrate that our technique is able to dynamically phase lock the PLA delays to the beat clock, across a wide range of PVT variations, enabling the sub-threshold design methodology to be applicable in practice. We also present an analysis of the loop gain of this closed-loop adaptive body biasing technique in Sect. 10.6.
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Jayakumar, N., Paul, S., Garg, R., Gulati, K., Khatri, S.P. (2010). Adaptive Body Biasing to Compensate for PVT Variations. In: Minimizing and Exploiting Leakage in VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0950-3_10
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DOI: https://doi.org/10.1007/978-1-4419-0950-3_10
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