Abstract
Configurable Computing is a technology which attempts to increase computational power by customizing the computational platform to the specific problem at hand. An experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. The Colt/Stallion project at Virginia Tech implements this computing model into integrated circuits. In order to create applications for this platform, a compiler has been implemented which utilizes a genetic algorithm in order to map dataflow graphs to the physical hardware of the Colt/Stallion chip. A description of the language is presented, followed by experimental results.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
E. Acosta, V. Bove, Jr., J. Wallington and R. Yu, “Reconfigurable Processor for a Data-Flow Video Processing System,” Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, J. Schewel, ed., SPIE-The International Society for Optical Engineering, Bellingham, Wash., 1995, pp. 83–91.
R. Bittner, M. Musgrove, and P. Athanas, “Colt: An Experiment in Wormhole Run-Time Reconfiguration,” High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (SPIE), Nov. 1996, pp. 187–194.
R. Bittner, “Wormhole Run-time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System,” doctoral dissertation, Virginia Tech, Bradley Department of Electrical and Computer Engineering, Jan. 1997.
J. Eldredge and B. Hutchings, “Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration,” Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D. Buell and K. Pocek, eds., Napa, Calif., April 1994, pp. 180–188.
D. Fogel, “An Introduction to Simulated Evolutionary Optimization”, IEEE Transactions on Neural Networks, Vol. 5, No. 1, Jan. 1994, pp. 3–8.
R. Hartenstein, J. Becker, and R. Kress, “Custom Computing Machines vs. Hardware/Software Co-Design: from a Globalized Point of View,” Sixth International Workshop of Field Programmable Logic and Applications, Lecture Notes in Computer Science, no. 1142, Springer-Verlag, Oxford, England, Sept. 1996, pp. 65–76.
K. Hwang, Advanced Computer Architecture, McGraw-Hill, New York, N.Y., 1993, pp. 442–446.
W. Luk, S. Guo, N. Shirazi, and N. Zhuang, “An Integrated Framework for Developing Parametrised Macros,” Sixth International Workshop of Field Programmable Logic and Applications, Lecture Notes in Computer Science, no. 1142, Springer-Verlag, Oxford, England, Sept. 1996, pp. 24–33.
S. Singh, J. Hogg, and D. McAuley, “Expressing Dynamic Reconfiguration by Partial Evaluation,” IEEE Symposium on FPGAs for Custom Computing Machines, D. Buell and K. Pocek, eds., Napa, Calif., April 1996, pp. 188–194.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1997 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kahne, B., Athanas, P. (1997). Stream synthesis for a wormhole run-time reconfigurable platform. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_215
Download citation
DOI: https://doi.org/10.1007/3-540-63465-7_215
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-63465-2
Online ISBN: 978-3-540-69557-8
eBook Packages: Springer Book Archive