Abstract
This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification and the gate-level network behavior by means of boolean functions. These functions are efficiently handled by using Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, the applicability of our verification method has been proven by checking the correctness of different benchmarks.
Work supported by CYCIT TIC 94-0531-E and Departament d'Ensenyament de la Generalitat de Catalunya.
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Roig, O., Cortadella, J., Pastor, E. (1995). Verification of asynchronous circuits by BDD-based model checking of Petri nets. In: De Michelis, G., Diaz, M. (eds) Application and Theory of Petri Nets 1995. ICATPN 1995. Lecture Notes in Computer Science, vol 935. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60029-9_50
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DOI: https://doi.org/10.1007/3-540-60029-9_50
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