Abstract
During the past decade, microprocessor peak performance has increased at a tremendous rate using RISC concept, higher and higher clock frequencies and parallel/pipelined instruction issuing. As the gap between the main memory access time and the potential average instruction time is always increasing, it has become very important to improve the behavior of the caches, particularly when no secondary cache is used (i.e on all low cost microprocessor systems). In order to improve cache hit ratios, set-associative caches are used in some of the new superscalar microprocessors.
In this paper, we present a new organization for a multi-bank cache: the skewed-associative cache. Skewed-associative caches have a better behavior than set-associative caches: typically a two-way skewed-associative cache has the hardware complexity of a two-way set-associative cache, yet simulations show that it exhibits approximatively the same hit ratio as a four-way set associative cache of the same size.
This work was partially supported by CNRS (PRC-ANM)
This is a preview of subscription content, log in via an institution.
Preview
Unable to display preview. Download preview PDF.
References
A. Agarwal, M. Horowitz, J. Hennesy “Cache performance of operating systems and multiprogramming work-loads” ACM Transactions on Computer Systems, Nov. 1988
A. Agarwal Analysis of Cache Performance for Operating Systems and Multiprogramming, Kluwer Academic Publishers, 1989
T.E. Anderson, H.M. Levy, B.N Bershad, E.D. Lazowska “The interaction of architecture and operating system design” Proceedings of ASPLOS IV, April 1991
M.D. Hill, “A case for direct-mapped caches”, IEEE Computer, Dec 1988
M.D.Hill, A.J. Smith “Evaluating Associativity in CPU Caches” IEEE Transactions on Computers, Dec. 1989
N.P. Jouppi, D.W. Wall “Available instruction-level parallelism for superscalar and superpipelined machines “ Proceedings of ASPLOS III, April 1989
N.P. Jouppi, “Improving Direct-Mapped Cache Performance by the addition of a Small Fully-Associative Cache and Prefetch Buffers” Proceedings of the 17th International Symposium on Computer Architecture, June 1990
M. Lam, E. Rothberg and M. Wolf, “The Cache Performance and Optimizations of Blocked Algorithms”, Proceedings of ASPLOS IV, April 91
J.R.Larus, “Abstract execution: a technique for Efficiently Tracing Programs” Technical Report, Computer Sciences Departement, University of Wisconsin-Madison, May 1990
J.C. Mogul, A. Borg “The effect of context switches on cache performance” Proceedings of ASPLOS IV, April 1991
A. Seznec, “A case for two-way skewed-associative caches”, Proceedings of the 20th International Symposium on Computer Architecture, May 1993
A. J. Smith “A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory” IEEE Transactions on Sofware Engineering, March 1978
A.J. Smith “Cache memories” ACM Computing Surveys, Sept. 1982
A.J. Smith “Line (block) size choice for CPU cache memories” IEEE Transactions on Computers, Sept. 1987
M.D. Smith, M. Johnson, M.A. Horowitz “Limits on multiple instruction issue” Proceedings of ASPLOS III, April 1989
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1993 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Seznec, A., Bodin, F. (1993). Skewed-associative caches. In: Bode, A., Reeve, M., Wolf, G. (eds) PARLE '93 Parallel Architectures and Languages Europe. PARLE 1993. Lecture Notes in Computer Science, vol 694. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56891-3_24
Download citation
DOI: https://doi.org/10.1007/3-540-56891-3_24
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-56891-9
Online ISBN: 978-3-540-47779-2
eBook Packages: Springer Book Archive