Abstract
In this paper we present a Neural Silicon Compiler (NSC) which is dedicated to the generation of Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural language. The integration of this tool into a neural network programming environment permits the translation of a neural application specified in the C-bascd input language into cither binary (for simulation) or silicon (for execution in hardware). The development of the NSC focuses on the high level synthesis part of thc silicon compilation process, where the output is a Register Transfer Level of a circuit specified in VHDL. This is accomplished through a heuristic approach, which targets the generated hardware structure of the ASNNCs in an optimised digital VLSI architecture employing bolh phases of neural computing on-chip: recall and learning.
Sponsored by the Brazilian Research Agency CNPq — Conselho Nacional de Desenvolvimento Científico e Technológico.
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© 1993 Springer-Verlag Berlin Heidelberg
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Nigri, M.E., Treleaven, P.C. (1993). High level synthesis of neural network chips. In: Mira, J., Cabestany, J., Prieto, A. (eds) New Trends in Neural Computation. IWANN 1993. Lecture Notes in Computer Science, vol 686. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56798-4_186
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DOI: https://doi.org/10.1007/3-540-56798-4_186
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