Abstract
In this study, we present a new concurrent error-detection scheme by hybrid signature to the on-line detection of control flow errors caused by transient and intermittent faults. The proposed hybrid signature monitoring technique combines the vertical signature scheme with the horizontal signature scheme. We first develop a new vertical signature scheme. The length of vertical signature is adjustable. The attribute of adjustable length can be employed to reduce the length of vertical signature, but at meantime it also decreases the coverage. The rest of signature word can be utilized for the horizontal signature and recording the block length. The horizontal signature can offset the coverage degradation due to the reduction of vertical signature length, and decrease the latency significantly. The simulation is conducted to justify the effectiveness of the proposed technique and compared with the previous schemes.
The main contribution of this research is to integrate the vertical signature, horizontal signature and watchdog timer techniques into a single signature word, and without the using of the memory system equipped with the SECDED code. Therefore, with no increase or even lower of memory space overhead and watchdog processor complexity, our scheme has higher errordetection coverage and much shorter error-detection latency compared with the previous representative techniques.
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References
M. Schmid, R. Trapp, A. Davidoff, and G. Masson, “ Upset exposure by means of abstraction verification, ” in Proc. 12th IEEE FTCS, 1982, pp. 237–244.
U. Gunneflo, J. Karlsson, and J. Torin, “ Evaluation of error detection schemes using fault injection by heavy-ion radiation,” in Proc. 19th IEEE FTCS, 1989, pp. 340–347.
M. Namjoo, “ Techniques for concurrent testing of VLSI processor operation, ” in Proc. 12th IEEE ITC, November 1982, pp. 461–468.
A. Mahmood, D. J. Lu, and E. J. McCluskey, “ Concurrent Fault Detection using a Watchdog Processor and Assertions, ” in Proc. 13th IEEE ITC, 1983, pp. 622–628.
A. Mahmood and E. J. McCluskey, “ Concurrent error detection using watchdog processor-A survey, ” IEEE Trans. on Computers, Vol. 37, No. 2, pp. 160–174, Feb. 1988.
J. Ohlsson, M. Rimen, and U. Gunneflo, “A Study of the Effects of Transient Fault Injection into a 32-bit RISC with Built-in Watchdog”, FTCS-22, 1992, pp. 316–325.
J. Ohlsson and M. Rimen, “Implicit Signature Checking”, FTCS-25, 1995, pp. 218–227.
K. Wilken and T. Kong, “Concurrent Detection of Software and Hardware Data-Access Faults”, IEEE Trans. on Computers, vol. 46, No. 4, pp. 412–424, April 1997.
I. Majzik, A. Pataricza et. al, “Hierarchical Checking of Multiprocessors Using Watchdog Processors”, EDCC-1, 1994, pp. 386–403.
T. Sridhar and S. M. Thatte, “ Concurrent Checking of Program Flow in VLSI processors,” in Proc. 12th IEEE ITC, 1982, pp. 191–199.
M. Schuette and J. Shen, “ Processor Control Flow Monitoring Using Signatured Instruction Streams, ” IEEE Trans. on Computers, Vol. C-36, No.3, pp.264–276, March 1987.
K. Wilken and J. Shen, “ Embedded Signature Monitoring: Analysis and Technique, ” in Proc. 17th IEEE ITC, 1987, pp. 324–333.
K. Wilken and J. Shen, “Continuous signature monitoring: Efficient concurrent detection of processor control errors, ” in Proc. 18th Int. Test Conf., 1988, pp. 914–925.
K. Wilken, J. Shen, “ Continuous Signature Monitoring: Low-Cost Concurrent Detection of Processor Control Errors, ” IEEE Trans. Computer-Aided Design, Vol. 9, No. 6, June 1990, pp. 629–641.
S. J. Upadhyaya, B. Ramamurthy, “ Concurrent Process Monitoring with No Reference Signatures, ” IEEE Trans. on Computers, Vol. 43, No. 4, pp. 475–480, April 1994.
A. Mahmood and E. J. McCluskey, “ Watchdog Processors: Error Coverage and Overhead,” in Proc. 15th IEEE FTCS, 1985, pp. 214–219.
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© 1999 Springer-Verlag Berlin Heidelberg
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Chen, YY. (1999). Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. In: Hlavička, J., Maehle, E., Pataricza, A. (eds) Dependable Computing — EDCC-3. EDCC 1999. Lecture Notes in Computer Science, vol 1667. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48254-7_29
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DOI: https://doi.org/10.1007/3-540-48254-7_29
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