Abstract
This paper presents CODACS (COnfigurable DAtaflow Computing System) architecture, a high performance reconfigurable computing system prototype with a highly scalable degree able to directly execute in hardware dataflow processes (dataflow graphs). The reconfigurable environment consists of a set of FPGA based platform- processors created by a set of identical Multi Purpose Functional Units (MPFUs) and a reconfigurable interconnect to allow a straightforward one-to-one mapping between dataflow actors and MPFUs. Since CODACS does not support the conventional processor cycle, the platform-processor computation is completely asynchronous according to the dataflow graph execution paradigm proposed in [8].
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Gray, J.P., Kean, T.A.: Configurable Hardware: A New Paradigm for Computation. In Proc. Decennial CalTech Conf. VLSI, pages 277–293, Pasadena, CA, March 1989.
Verdoscia, L., Licciardo, G.: CODACS Project: The General Architecture and its Motivation. Technical report, CNR Research Center on Parallel Computing and Supercomputers, Via Castellino, 111-80131 Napoli-Italy, January 2002.
Chen, G.H., Du, D.R.: Topological Properties, Communication, and Computing on WK-Recursive Networks. Networks, 24:303–317, 1994.
Verdoscia, L., Vaccaro, R.: An Adaptive Routing Algorithm for WK-Recursive Topologies. Computing, 63(2):171–184, 1999.
ALTERA Corporation.: Quartus programmable logic development system and software. San Jose, CA, May 1999.
Singh, H., alii.: Morphosys: An Integrated Reconfigurable System for Data-Parallel and Computation Intensive Applications. IEEE Trans. Computers, 49(5):465–480, May 2000.
Murakawa, M., alii.: The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. IEEE Trans. on Computers, 48(6):628–639, June 1999.
Verdoscia, L., Vaccaro, R.: A High-Level Dataflow System. Computing, 60(4):285–305, 1998.
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Verdoscia, L. (2002). CODACS Project: A Demand-Data Driven Reconfigurable Architecture. In: Monien, B., Feldmann, R. (eds) Euro-Par 2002 Parallel Processing. Euro-Par 2002. Lecture Notes in Computer Science, vol 2400. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45706-2_74
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DOI: https://doi.org/10.1007/3-540-45706-2_74
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