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MAJC-5200: A High Performance Microprocessor for Multimedia Computing

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Parallel and Distributed Processing (IPDPS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1800))

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Abstract

The newly introduced Microprocessor Architecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip, vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The first implementation, MAJC-5200, includes some key features of MAJC to realize a high performance multimedia processor. Two CPUs running at 500 MHz are integrated into the chip to provide 6.16 GFLOPS and 12.33 GOPS with high speed interfaces providing a peak input-output (I/O) data rate of more than 4.8 G Bytes/second. The chip is suitable for a number of applications including graphics/multimedia processing for high-end set-top boxes, digital voice processing for telecomm unications, and advanced imaging.

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References

  1. M. Tremblay “A microprocessor architecture for the new millennium,” Hot Chips 11, Palo Alto, CA, August 1999.

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Author information

Authors and Affiliations

  1. Sun Microsystems, Inc., Palo Alto, CA, 94303, USA

    Subramania Sudharsanan

Authors
  1. Subramania Sudharsanan
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Editor information

Editors and Affiliations

  1. Centre Universitaire d’Informatique, Université de Genève, 24, rue Général Dufour, CH-1211, Genève 4, Switzerland

    José Rolim

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© 2000 Springer-Verlag Berlin Heidelberg

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Sudharsanan, S. (2000). MAJC-5200: A High Performance Microprocessor for Multimedia Computing. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_22

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  • DOI: https://doi.org/10.1007/3-540-45591-4_22

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67442-9

  • Online ISBN: 978-3-540-45591-2

  • eBook Packages: Springer Book Archive

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