Abstract
We present TEM2P2EST, a flexible, cycle-accurate microarchitectural power/performance analysis tool based on SimpleScalar. The goal was to build a “flexible” simulation tool, incorporating several estimation models and providing a scalable framework for future development. This approach is based on the fact that different power models have different tradeoffs in terms of power estimation accuracy and flexibility/scalability. The simulator generates power estimates based on either empirical data or analytical models. In future, other modes like estimation based on RTL extraction can be included. The tool includes analytical models for dynamic and leakage power, di/dt power, dual Vt support and process technology scaling options. It has a thermal model built to study thermal issues and techniques like clock throttling. Initial studies show that our results are consistent and match well with real design simulated with SPICE. In addition, we validated our temperature model with measurement on a typical microprocessor heat solution.
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References
R. Gonzales and M. Horowitz. Energy Dissipation in General Purpose Processors. In Proc. Of International Symposium on Low-Power Electronics and Design, 1995.
M. K. Gowan, L. L. Biro, and D. B. Jackson. Power Considerations in the Design of the Alpha 21264 Microprocessor. In 35 th Design Automation Conference, 1998.
Best New Technology: Power4. Microprocessor Report, Feb. 2000.
V. De and S. Borkar. Technology and Design Challenges for Low-Power and High Performance. In Proc. of the International Symposium on Low-Power Electronics and Design, 1999.
A. Chatterjee, M. Nandakumar, and I. Chen. An Investigation of Technology Scaling on Power Wasted as Short-Circuit Current in Low Voltage Static CMOS Circuits. In Proc. of the International Symposium on Low-Power Electronics and Design, 1996.
D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June 1997.
P. Landman and J. Rabaey. Activity-Sensitive Architectural Power Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(6), page 571, Jun. 1996.
R. Chen, M. Irwin, and R. Bajwa. An architectural level power estimator. In Power-Driven Microarchitecture Workshop at ISCA25, 1998.
M.B. Kamble and K. Ghose. Analytical Energy Dissipation Models for Low Power Caches. In Proc. of International Symposium on Low-Power Electronics and Design, 1997.
R. Iris Bahar, G. Albera, and S. Manne. Power and Performance Tradeoffs using Various Caching Strategies. In Proc. of International Symposium on Low-Power Electronics and Design, 1998.
S. Palacharla, N. Jouppi, and J. Smith. Complexity-Effective Superscalar Processors. In Proc. of the 24 th International Symposium on Computer Architecture, 1997.
T. Sato, M. Nagamatsu, and H. Tago. Power and Performance Simulator: ESP and its Application for 100MIPS/W Class RISC Design. In Proc. of the International Symposium on Low Power Electronics, 1994.
G. Cai and C. H. Lim. Architectural level power/performance optimization and dynamic power estimation, Cool Chips tutorial at MICRO 32, November 1999.
D. Brooks, V. Tiwari and M. Martonosi. Wattch: A framework for Architectural-Level Power Analysis and Optimization. In Proc. of the 27 th International Symposium on Computer Architecture, 2000.
W. Ye, N. Vijaykrishnan, M. Kandemir, and M. Irwin. The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool. In Proc. Of Design Automation Conference, 2000.
S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-chip Caches. In WRL Research Report 93/5, DEC Western Research Laboratory, 1994.
V. Zyuban and P. Kogge. The Energy Complexity of Register Files. In Proc. of International Symposium on Low-Power Electronics and Design, pp. 305–310, 1998.
B. Bishop, T. Kelliher, and M. Irwin. The design of a Register Renaming Unit. In Proc. of Great Lakes Symposium on VLSI, 1999.
N. Gaddis, J. Butler, A. Kumar, and W. Queen. A 56-Entry Instruction Reorder Buffer, In Proc. of the International Solid-State Circuits Conference, 1996.
T. Kobayashi, et. al. Thermal Design of an Ultraslim Notebook Computer. IEEE Transactions on Components and Packaging Technologies, Vol. 23, No. 1, March 2000.
J. de Vegte, Feedback Control System, 3rd. Edition, Prentice Hall: New Jersey, 1994.
S. Ghiasi and Dirk Grunwald, A Comparison of Two Architectural Power Models, PACS 2000, Nov. 2000.
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Dhodapkar, A., How Lim, C., Cai, G., Robert Daasch, W. (2001). TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2000. Lecture Notes in Computer Science, vol 2008. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44572-2_9
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DOI: https://doi.org/10.1007/3-540-44572-2_9
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