Abstract
This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS’89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.
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Chakraborty, D., Chakrabarti, P.P., Mondal, A., Dasgupta, P. (2006). A Framework for Estimating Peak Power in Gate-Level Circuits. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_56
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DOI: https://doi.org/10.1007/11847083_56
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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