Abstract
In this paper, we present a formal modeling and refinement approach for on-chip communication architecture development, based on the Action Systems formalism. Stepwise refinement from an abstract high-level initial model to an implementable parallel switch based model is discussed. The focus is on gradually decomposing the initial specification into a composition of concurrently operating subsystems. Data transactions are modelled with atomic message passing events via interface procedures, for which a new notation is introduced. The concept is demonstrated by a network-like pipelined bus platform.
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Plosila, J., Liljeberg, P., Isoaho, J. (2005). Modelling and Refinement of an On-Chip Communication Architecture. In: Lau, KK., Banach, R. (eds) Formal Methods and Software Engineering. ICFEM 2005. Lecture Notes in Computer Science, vol 3785. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11576280_16
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DOI: https://doi.org/10.1007/11576280_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29797-0
Online ISBN: 978-3-540-32250-4
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