Abstract
The complexity of SoC is increasing rapidly. It is an important trend that SoC design is always based on the reuse of both IP cores and software components. In consequence, new verification techniques are needed, which overcome the limitations of traditional methods and are suitable for SoC at the same time. This paper introduces a computational model for SoC based on colored Petri net, formulates the IP cores, components and user defined logics, and presents a method to translate the architecture design into the colored Petri net model. And a formal co-verification approach of SoC using CPN tools is also proposed. The method concentrates on verifying the correctness of the design. An example of the audio and video architecture design of the PDA platform illustrates the effectiveness of our approach on practical applications. Finally, the experimental results are given.
This work was supported by the National High Technology Research and Development Program (863), under Grant No. 2003AA1Z2210.
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Online: CPN Tools, http://wiki.daimi.au.dk/cpntools/
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Zhan, J., Sang, N., Xiong, G. (2005). Formal Co-verification for SoC Design with Colored Petri Net. In: Wu, Z., Chen, C., Guo, M., Bu, J. (eds) Embedded Software and Systems. ICESS 2004. Lecture Notes in Computer Science, vol 3605. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535409_26
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DOI: https://doi.org/10.1007/11535409_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28128-3
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