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Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems

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Abstract

In this paper, we combine coarse-grained software pipelining with DVS (Dynamic Voltage/Frequency Scaling) for optimizing energy consumption of stream-based multimedia applications on multi-core embedded systems. By exploiting the potential of multi-core architecture and the characteristic of streaming applications, we propose a two-phase approach to solve the energy minimization problem for periodic dependent tasks on multi-core processors with discrete voltage levels. With our approach, in the first phase, we propose a coarse-grained task-level software pipelining algorithm called RDAG to transform the periodic dependent tasks into a set of independent tasks based on the retiming technique (Leiserson and Saxe, Algorithmica 6:5–35, 1991). In the second phase, we propose two DVS scheduling algorithms for energy minimization. For single-core processors, we propose a pseudo-polynomial algorithm based on dynamic programming that can achieve optimal solution. For multi-core processors, we propose a novel scheduling algorithm called SpringS which works like a spring and can effectively reduce energy consumption by iteratively adjusting task scheduling and voltage selection. We conduct experiments with a set of benchmarks from E3S (Dick 2008) and TGFF (http://ziyang.ece.northwestern.edu/tgff/) based on the power model of the AMD Mobile Athlon4 DVS processor. The experimental results show that our technique can achieve 12.7% energy saving compared with the algorithms in Zhang et al. (2002) on average.

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Authors and Affiliations

  1. Software Engineering Institute, Xidian University, Xi’an, 710071, China

    Hui Liu & Junzhao Du

  2. Department of Computing, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong

    Zili Shao & Meng Wang

  3. Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong

    Chun Jason Xue

  4. School of Computer Science and Technology, Shandong University, Jinan, China

    Zhiping Jia

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  1. Hui Liu
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  2. Zili Shao
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  3. Meng Wang
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  4. Junzhao Du
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Correspondence to Zili Shao.

Additional information

This work is partially supported by the grants from the Research Grants Council of the Hong Kong Special Administrative Region, China (CERG 526007 (PolyU B-Q06B), PolyU A-PH41), Shaanxi Administration of Foreign Expert Affairs under grant No. 2007-38/DF0105072301, Intel-Xidian Multicore Technology Lab, and the National Science Foundation of China (No.90718032).

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Liu, H., Shao, Z., Wang, M. et al. Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems. J Sign Process Syst Sign Image Video Technol 57, 249–262 (2009). https://doi.org/10.1007/s11265-008-0315-2

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