Skip to main content
SpringerLink
Log in

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Notes

  1. Given the two major FPGA companies are based on the USA.

  2. ERC32 is a discontinued radiation-tolerant SPARC V7 processor developed for space applications.

  3. Experimenting on the spreadsheet, less than 0.5mW difference on the dynamic power was noticed for the 1500 and 3000 device.

References

  1. Aeroflex Gaisler: GRLIB IP Library (2015a) http://www.gaisler.com/index.php/products/ipcores/soclibrary

  2. Aeroflex Gaisler: LEON3 Processor (2015b) http://www.gaisler.com/index.php/products/processors/leon3

  3. Aeroflex Gaisler: LEON3FT-RTAX Fault-tolerant Processor (2015c) http://www.gaisler.com/index.php/products/components/leon3ft-rtax

  4. Alkhafaji FSM, Hasan WZW, Isa MM, Sulaiman N (2018) Robotic controller: ASIC versus FPGA - a review. J Comput Theor Nanosci 15(1):1–25

    Article  Google Scholar 

  5. Altera Tech. (2013) White paper: Introduction to single-event upsets

  6. Argyrides C, Pradhan DK, Kocak T (2011) Matrix Codes for Reliable and Cost Efficient Memory Chips, vol 19. https://doi.org/10.1109/TVLSI.2009.2036362. http://ieeexplore.ieee.org/document/5352255/

  7. Avizienis A, Laprie JC, Randell B, Landwehr C (2004) Basic concepts and taxonomy of dependable and secure computing. IEEE Trans Dependable Secure Comput 1(1):11–33. https://doi.org/10.1109/TDSC.2004.2. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1335465

    Article  Google Scholar 

  8. Barboza SHI, Bregant M, Chambert V, Espagnon B, Herrera HDH, Mahmood SM, Moraes D, Munhoz MG, Noėl G, Pilyar a et al (2016) SAMPA chip: a new ASIC for the ALICE TPC and MCH upgrades. J Instrum 11(02):C02,088

    Article  Google Scholar 

  9. Barnaby HJ (2006) Total-Ionizing-Dose Effects in Modern CMOS Technologies, vol 53. https://doi.org/10.1109/TNS.2006.885952. http://ieeexplore.ieee.org/document/4033191/

  10. Battezzati N, Sterpone L, Violante M (2010) Reconfigurable field programmable gate arrays for mission-critical applications. Springer, Berlin. https://books.google.com.br/books?hl=en&lr=&id=iVScPZCgp_EC&oi=fnd&pg=PP5&dq=reconfigurable+field+programmable+gate+arrays+for+mission-critical+applications&ots=fjBZtSQupc&sig=jx3fKoLJ61msyfpPwqZJVTtT5lo

    Google Scholar 

  11. Baumann R (2003) Impact of Single-Event Upsets in Deep-Submicron Silicon Technology. https://doi.org/10.1557/mrs2003.38. http://journals.cambridge.org/abstract_S0883769400017516

  12. Bernardeschi C, Cassano L, Domenici A (2015) SRAM-based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies. J Comput Sci Technol 30(2):373–390. https://doi.org/10.1007/s11390-015-1530-5

    Article  Google Scholar 

  13. Bouhali M, Shamani F, Dahmane ZE, Belaidi A, Nurmi J (2017) FPGA applications in unmanned aerial vehicles - a review. In: Wong S, Beck AC, Bertels K, Carro L (eds) Proceedings of Applied reconfigurable computing. Springer International Publishing, Cham, pp 217–228

  14. Castro HdS, da Silveira JAN, Coelho AAP, e Silva FGA, Magalhaes PdS, de Lima OA (2016) A correction code for multiple cells upsets in memory devices for space applications. In: Proceedings of 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, pp 1–4. https://doi.org/10.1109/NEWCAS.2016.7604783. http://ieeexplore.ieee.org/document/7604783/

  15. Cetin E, Diessel O, Li T, Ambrose JA, Fisk T, Parameswaran S, Dempster AG (2016) Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems. In: Proceedings of the FPGAs and Parallel Architectures for Aerospace Applications. Springer International Publishing, Cham, pp 33–46. https://doi.org/10.1007/978-3-319-14352-1_3

  16. de Oliveira AB, Tambara LA, Kastensmidt FL (2017) Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors. In: Proceedings of the 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, pp 1–4. https://doi.org/10.1109/LASCAS.2017.7948063. http://ieeexplore.ieee.org/document/7948063/

  17. EEJournal: The Biggest SoC/FPGAs (2017). https://www.eejournal.com/article/the-biggest-socfpgas/

  18. Ferlini F, da Silva FA, Bezerra E, Lettnin DV (2012) Non-intrusive fault tolerance in soft processors through circuit duplication. In: Proceedings of 2012 13th Latin American Test Workshop (LATW). IEEE, pp 1–6. https://doi.org/10.1109/LATW.2012.6261264. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6261264

  19. Friend RB, Arroyo C, Hansen J (2016) Big Missions, Small Solutions Advances and Innovation in Architecture and Technology for Small Satellites. In: Proceedings of the AIAA SPACE 2016. American Institute of Aeronautics and Astronautics, Reston, Virginia. https://doi.org/10.2514/6.2016-5229

  20. Glein R (2014) BRAM radiation sensor for a Self-Adaptative SEU mitigation. In: Proceedings of the Space FPGA users workshop

  21. Goloubeva O, Rebaudengo M, Reorda M, Violante M (2006) Software-implemented hardware fault tolerance. Springer, Berlin. https://books.google.com.br/books?hl=en&lr=&id=qX9GAAAAQBAJ&oi=fnd&pg=PA1&dq=software+implemented+hardware+fault-tolerance&ots=owaXCAdHzD&sig=G5Ql7eRDVfTwvyZRIrP4zYxQsw8

    MATH  Google Scholar 

  22. Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) Mibench: a free, commercially representative embedded benchmark suite. In: Proceedings of 2001 IEEE international workshop workload characterization, WWC’01. IEEE Computer Society, Washington, pp 3–14. https://doi.org/10.1109/WWC.2001.15

  23. Guzman-Miranda H, Aguirre M, Tombs J (2009) Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors, vol 58. https://doi.org/10.1109/TIM.2009.2014603 https://doi.org/10.1109/TIM.2009.2014603. http://ieeexplore.ieee.org/document/4787115/

  24. Guzmȧn D, Rowland D, Uribe P, Nieves T (2011) A Low Power Processors for Cubesat Missions. In: Proceedings of the 8th annual cubesat developer’s workshop 2011

  25. Henkel J, Bauer L, Dutt N, Gupta P, Nassif S, Shafique M, Tahoori M, Wehn N (2013) Reliable On-chip Systems in the Nano-era: Lessons Learnt and Future Trends. In: Proceedings of the 50th annual design automation conference, DAC’13. ACM, New York, pp 99:1–99:10. https://doi.org/10.1145/2463209.2488857

  26. Kastensmidt FL, Fonseca ECP, Vaz RG, Goncalez OL, Chipana R, Wirth GI (2011) TID in Flash-Based FPGA: Power Supply-Current Rise and Logic Function Mapping Effects in Propagation-Delay Degradation. IEEE Trans Nuclear Sci 58(4):1927–1934. https://doi.org/10.1109/TNS.2011.2128881. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5752883

    Article  Google Scholar 

  27. Keller AM, Wirthlin MJ (2017) Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs. IEEE Trans Nuclear Sci 64(1):519–528. https://doi.org/10.1109/TNS.2016.2635028. http://ieeexplore.ieee.org/document/7763831/

    Article  Google Scholar 

  28. Kletzing CA, Kurth WS, Acuna M, MacDowall RJ, Torbert RB, Averkamp T, Bodet D, Bounds SR, Chutter M, Connerney J, Crawford D, Dolan JS, Dvorsky R, Hospodarsky GB, Howard J, Jordanova V, Johnson RA, Kirchner DL, Mokrzycki B, Needell G, Odom J, Mark D, Pfaff R, Phillips JR, Piker CW, Remington SL, Rowland D, Santolik O, Schnurr R, Sheppard D, Smith CW, Thorne RM, Tyler J (2013) The electric and magnetic field instrument suite and integrated science (EMFISIS) on RBSP. Space Sci Rev 179(1-4):127–181. https://doi.org/10.1007/s11214-013-9993-6

    Article  Google Scholar 

  29. Koren I, Krishna C (2010) Fault-tolerant systems. Morgan Kaufmann, San Mateo. https://books.google.com.br/books?hl=en&lr=&id=oPjbo4Wvp8C&oi=fnd&pg=PR11&dq=fault+tolerant+systems+koren&ots=RYPEQBzbyA&sig=pMKkYxL70ahe4U4U3hTKWLlrR3Y

    MATH  Google Scholar 

  30. Lesage L, Mejias B, Lobelle M (2011) A software based approach to eliminate all SEU effects from mission critical programs. In: Proceedings of the 2011 12th European Conference on Radiation and Its Effects on Components and Systems. IEEE, pp 467–472. https://doi.org/10.1109/RADECS.2011.6131353. http://ieeexplore.ieee.org/document/6131353/

  31. Li T, Shafique M, Ambrose JA, Henkel J, Parameswaran S (2017) Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans Comput 66(4):647–660. https://doi.org/10.1109/TC.2016.2606378. http://ieeexplore.ieee.org/document/7562290/

    Article  MathSciNet  MATH  Google Scholar 

  32. Lindoso A, Entrena L, Garcia-Valderas M, Parra L (2017) A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA. IEEE Trans Nuclear Sci 64(1):374–381. https://doi.org/10.1109/TNS.2016.2636574. http://ieeexplore.ieee.org/document/7776886/

    Article  Google Scholar 

  33. Martins VMG, Villa PRC, Neto HCC, Bezerra E (2015) A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow. In: Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE, pp 161–166. https://doi.org/10.1109/ISVLSI.2015.84. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7309556 http://ieeexplore.ieee.org/document/7309556/

  34. Microsemi Inc. (2017) ProASIC3 FPGA. https://www.microsemi.com/products/fpga-soc/fpga/proasic3-overview

  35. Microsemi Inc. (2018) Power Estimators and Calculators. https://www.microsemi.com/products/fpga-soc/design-resources/power-calculator

  36. Mogollon J, Guzman-Miranda H, Napoles J, Barrientos J, Aguirre M (2011) FTUNSHADES2: A novel platform for early evaluation of robustness against SEE. In: Proceedings of the 2011 12th European Conference on Radiation and Its Effects on Components and Systems. IEEE, pp 169–174. https://doi.org/10.1109/RADECS.2011.6131392. http://ieeexplore.ieee.org/document/6131392/

  37. Norton CD, Werne TA, Pingree PJ, Geier S (2009) An evaluation of the Xilinx Virtex-4 FPGA for on-board processing in an advanced imaging system. In: Proceedings of the 2009 IEEE Aerospace conference. IEEE, pp 1–9. https://doi.org/10.1109/AERO.2009.4839460. http://ieeexplore.ieee.org/abstract/document/4839460/

  38. Petkov M (2003) The effects of space environments on electronic components. In: JPL Technical Report Server 1992+. https://trs.jpl.nasa.gov/handle/2014/7193

  39. Ragel R, Parameswaran S (2012) Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. In: Proceedings of the 2012 Design, Automation & Test in Europe Conference &Exhibition (DATE). IEEE, pp 875–880. https://doi.org/10.1109/DATE.2012.6176621. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6176621

  40. Reorda M, Violante M, Meinhardt C, Reis R (2009) A low-cost SEE mitigation solution for soft-processors embedded in Systems on Programmable Chips. In: 2009 Design, Automation & Test in Europe Conference & Exhibition, pp 352–357. https://doi.org/10.1109/DATE.2009.5090687. http://dl.acm.org/citation.cfm?id=1874620.1874704

  41. Rodriguez-Andina JJ, Valdes-Pena MD, Moure MJ (2015) Advanced Features and Industrial Applications of FPGAs—A Review. IEEE Trans Ind Inf 11(4):853–864. https://doi.org/10.1109/TII.2015.2431223. http://ieeexplore.ieee.org/document/7104117/

    Article  Google Scholar 

  42. Sabena D, Sterpone L, Scholzel M, Koal T, Vierhaus HT, Wong S, Glein R, Rittner F, Stender C, Porrmann M, Hagemeyer J (2014) Reconfigurable high performance architectures: How much are they ready for safety-critical applications? In: Proceedings of the 2014 19th IEEE European Test Symposium (ETS). IEEE, pp 1–8. https://doi.org/10.1109/ETS.2014.6847820. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6847820

  43. Siegle F, Vladimirova T, Ilstad J, Emam O (2015) Mitigation of radiation effects in SRAM-based FPGAs for space applications. ACM Comput Surv 47(2):34. https://doi.org/10.1145/2671181. Article 37

    Article  Google Scholar 

  44. Siewiorek D, Swarz R (2017) Reliable computer systems: Design and evaluatuion. Digital Press

  45. Li T, Ambrose JA, Parameswaran S (2016) ReCoRD: Reducing Register Traffic for Checkpointing in Embedded Processors. In: Proceedings of the 2016 Conference on Design, Automation & Test in Europe, DATE’16. EDA Consortium, San Jose, pp 582–587. http://dl.acm.org/citation.cfm?id=2971808.2971945, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7459379

  46. Tang HH, Olsson N (2003) Single-Event Upsets in Microelectronics. MRS Bullet 28(02):107–110. http://journals.cambridge.org/abstract_S0883769400017498

    Article  Google Scholar 

  47. Torrens G (2017) FPGA-SRAM Soft Error Radiation Hardening. In: Field - Programmable Gate Array. InTech. https://doi.org/10.5772/66195 https://doi.org/10.5772/66195. http://www.intechopen.com/books/field-programmable-gate-array/fpga-sram-soft-error-radiation-hardening

  48. Travessini R, Villa PRC, Vargas F, Bezerra E (2018) Processor core profiling for SEU effect analysis. In: Proceedings of the 2018 IEEE 19th Latin-American Test Symposium (LATS). IEEE, pp 1–6. https://doi.org/10.1109/LATW.2018.8347235. https://ieeexplore.ieee.org/document/8347235/

  49. U.S. State Department (2018) Directorate of Defense Trade Controls. http://pmddtc.state.gov/index.html

  50. Velazco R, Fouillat P, Reis R (eds) (2007) Radiation Effects on Embedded Systems. Springer, Netherlands. https://doi.org/10.1007/978-1-4020-5646-8

  51. Villa P, Bezerra E, Goerl R, Poehls L, Vargas F, Medina N, Added N, De Aguiar V, MacChione E, Aguirre F, Da Silveira M (2017a) Analysis of COTS FPGA SEU-sensitivity to combined effects of conducted-EMI and TID. In: Proceedings of the 2017 11th international workshop on the electromagnetic compatibility of integrated circuits, EMCCompo 2017. https://doi.org/10.1109/EMCCompo.2017.7998076

  52. Villa PRC, Goerl RC, Vargas F, Poehls LB, Medina NH, Added N, de Aguiar VAP, Macchione ELA, Aguirre F, da Silveira MAG, Bezerra E Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. In: Proceedings of the 2017 18th IEEE Latin American Test Symposium (LATS). (2017b), pp 1–4. IEEE. https://doi.org/10.1109/LATW.2017.7906772. http://ieeexplore.ieee.org/document/7906772/

  53. Villa PRC, Travessini R, Vargas F, Bezerra E (2018) Processor checkpoint recovery for transient faults in critical applications. In: proceedings of the 2018 IEEE 19th Latin-American Test Symposium (LATS). IEEE, pp 1–6. https://doi.org/10.1109/LATW.2018.8349674. https://ieeexplore.ieee.org/document/8349674/

  54. Violante M, Meinhardt C, Reis R, Reorda MS (2011) A Low-Cost Solution for Deploying Processor Cores in Harsh Environments, vol 58. https://doi.org/10.1109/TIE.2011.2134054. http://ieeexplore.ieee.org/document/5740344/

  55. Wilson DS (2011) Cubesat Flight Software Development. In: Proceedings of the 2011 workshop on spacecraft flight software (FSW11). Baltimore

  56. Ziade H, Ayoubi RA, Velazco R, et al (2004) A survey on fault injection techniques. Int Arab J Inf Technol 1(2):171–186

    Google Scholar 

Download references

Acknowledgments

This work has been partly funded by the Brazilian National Council for Scientific and Technological Development (CNPq) and Instituto Federal do Rio Grande do Sul (IFRS).

Author information

Authors and Affiliations

  1. Federal Institute of Rio Grande do Sul, Veranópolis, Brazil

    Paulo R. C. Villa

  2. Electrical Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil

    Rodrigo Travessini

  3. Electrical Engineering Department, Catholic University - PUCRS, Porto Alegre, Brazil

    Roger C. Goerl & Fabian L. Vargas

  4. Electrical Engineering Department, UFSC, Brazil and LIRMM, Université de Montpellier, Montpellier, France

    Eduardo A. Bezerra

Authors
  1. Paulo R. C. Villa
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rodrigo Travessini
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Roger C. Goerl
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Fabian L. Vargas
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Eduardo A. Bezerra
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Paulo R. C. Villa.

Additional information

Responsible Editor: L. M. Bolzani Pöhls

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Villa, P.R.C., Travessini, R., Goerl, R.C. et al. Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. J Electron Test 35, 9–27 (2019). https://doi.org/10.1007/s10836-019-05778-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05778-z

Keywords

Search

Navigation