SMAC: A VLSI Architecture for Scene Matching

doi:10.1006/rtim.1998.0093

Real-Time Imaging

Volume 4, Issue 3, June 1998, Pages 171-180

https://doi.org/10.1006/rtim.1998.0093 Get rights and content

Abstract

Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. In this paper, we describe an efficient architecture for scene matching called SMAC (Scene Matching ArChitecture). The architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. Such an architecture can be used to compute the exhaustive search task of hierarchical scene matching, a technique used to reduce the amount of computations involved in scene matching applications. A prototype very large scale integration (VLSI) chip implementing a scaled down version of the proposed architecture has been designed and built. The prototype chip has been tested to be fully functional at a frequency of 50 MHz with a clock cycle of 20 ns. Based on the prototype design, it is estimated that the proposed architecture can process a 512 × 512 image with an 128 × 128 size template in about 15.36 μs, which corresponds to a rate of 65K frames per second.

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^☆: This research has been supported in part by the National Science Foundation Grant No. MIP-9407034

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Regular ArticleSMAC: A VLSI Architecture for Scene Matching☆

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Regular Article
SMAC: A VLSI Architecture for Scene Matching☆