Design architecture and performance measurements of a low noise, 128-channel application-specific-integrated-circuit (ASIC) preamplifier are reported. The ASIC was designed for readout of active matrix flat-panel imager (AMFPI) arrays. Such arrays, which presently can be made as large as 41 cm×41 cm and with pixel-to-pixel pitches down to 70 μm, require large numbers of low noise, high density, custom integrated readout circuits. The design of this new chip is specifically tailored for research and development of active matrix flat-panel arrays for various medical imaging applications. The design architecture includes the following features: (1) Programmable signal gain which allows acquisition of a wide range of signal sizes from various array designs so as to optimize the signal-to-noise ratio; (2) Correlated double sampling (CDS) which significantly reduces certain noise components; (3) Pipelined readout (simultaneously sampling and multiplexing signals) which reduces image acquisition time; (4) Programmable bandwidth controls which balance noise and acquisition speed; and (5) Two selectable modes of output multiplexing (64:1, 16:1) for slow or fast readout. In this paper, detailed measurements of various performance parameters are presented. These measurements include noise characteristics, the relationship between bandwidth and noise, signal response linearity, channel-to-channel and pipeline cross-talk, signal gain and gain variation across channels, and the effect of sampling methods on noise. These characterizations indicate that the performance of the ASIC has achieved the original design goals.