Abstract

This paper presents a new parallel algorithm for binary object skeletonization and its implementation in VLSI. The proposed skeletonization algorithm is based on a digital geometry concept known as the 'Voronoi diagram, which is established, after an edge detection pre-processing step, through the time evolution of Cellular Automata. The proposed algorithm is both space and time efficient, since it does not require any distance calculations and ordering of distances as in the case of other skeletonization algorithms nor the application of complex 'template' criteria to guarantee object connectiveness as in the case of thinning algorithms. Additionally, the proposed Cellular Automaton architecture achieves high frequency of operation and it is especially suited for VLSI implementation due to its inherent parallelism, structural locality, regularity and modularity. A set of quantitative measures was defined in this paper in order to evaluate the performance of the proposed algorithm. It was found that the proposed algorithm for pattern skeletonization outperforms already existing algorithms, with respect to these measures.